Ja scheint so: das LED-Bild mit...
0000*00* Test 16 Initiates memory tests Resident memory + Self test error report / CPU
... passt nicht zum häufiger auftretenden Fehler beim Memory Path Data Test, auch Bestandteil des Memory Test
Memory Path Data Test
Err 2: Addr 0x00000404, Exp 0x00000000, Obs 0x20000000, Xor 0x20000000
bzw.
Memory Path Data Test
Err 2: Addr 0x00000400, Exp 0x00000001, Obs 0x20000001, Xor 0x20000000
Da hätte ich sowas erwartet...
***0000* Test 7 Checking memory data path resident momory + Self test error report / CPU
Die Adresse des Parity Error könnte durchaus auf einen DIP im zweite MByte zeigen
1 megabyte = 0x00100000 = 1048576 bytes
megabyte #1 = 0x00000000..0x000FFFFF
megabyte #2 = 0x00100000..0x001FFFFF -> 0x00186814
megabyte #3 = 0x00200000..0x002FFFFF
megabyte #4 = 0x00300000..0x003FFFFF
Zitat von 800-1386-13 2060 CPU Engineering Manual
S.25 (doc p.4)
1.8 Device Space
The device space including everything accessed through the MMU - main memory, [...]
S.26 (doc p.5)
1.9 Memory Space (TYPE-0 space)
Main memory is implemented as described in section [5.2]. A positive acknowledge scheme is used so that non-existent memory locations result in a timeout bus error.
120 nsec 256K-by-1 DRAMs are used to implement the parity memory.
Accesses to this memory incure 1.5 wait states on reads and writes. There is a minimum of two megabytes of memory on the CPU board (a maximum of 4 megabytes) [...]
S.34 (doc p.16)
3.1 Data Paths
[...] The 32-bit bus provides a high-bandwidth path between CPU, DVMA devices and main memory. [...]
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Zitat von Sun-3 Customer Maintenance Training Sep88
Seiten 4-7 bis 4-10
The final two tests executed under the self test mode are for memory. The memory checks consist of a memory sizing test, and then a memory test. The parameters for these two test can be specified (set) by the EEPROM. in NORM the amount of memory tested can be specified in location 0x15. However in DIAG mode, all memory found will be tested regardless of the value in 0x15.
The following chart illustrates the sequence of events that take place during the memory phase of the self test.
[...]
2. MEMORY TEST- begins by:
a. initializes the ctx reg, seg map, page map with virtual mapped directly to physical addresses then.
b. performs consecutive write then read then compare passes to the memory under test and
c. services any parity error interrupts.
d. displays any memory errors- found as
Error: addr 000000n, exp 000000n, obs 000000n
Memory parity err, addr 000000n, exp 000000n
The following table lists the sequence of tests accomplished by the self tests, their display patterns, and the logic most likely causing the fault.Failure will be indicated with the test number latched up and the most significant bit latched on. Occasionally a test will indicate a failure by going into an infinite loop and not latching up MSB. This is indicated by a constantly repeating pattern in the LED display and (if enabled) a repeating pattern of tests on the ASCII terminal.
(LSB Least-Significant-Bit -> MSB Most-Significant-Bit)
[...]
8. MEMORY PATH DATA TEST-tests the path between the CPU and DRAMS
by writing then reading the lowest portion of memory with shifting 1 's
patterns (this is the first CPU to memory path test).
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NACHTRAG:
Du könntest im Diag-Switch NORM starten und die EEPROM Pos 0x15 (# MB for selftest) auf 1MB begrenzen (wenn das überhaupt geht), dann den Memory Test durchführen. Wenn da keine Fehler auftauchen, also weder beim Memory Path Data Test noch Parity Test. ist das ... i.O. (?) (das ist aber auch kompliziert)
Der "Fehlerstecker" ist für mich im ersten, nicht im zweiten MByte aufgesteckt. Wenn du nach dem Schema ^ mit absoluten Positionen gehst, sollte dann dieser gebastelte Fehlerstecker nicht eher bei einem DRAM in der Reihe S..T anliegen?